1. Field of the Invention
The present invention relates generally to split gate field effect transistor (FET) devices, as fabricated within semiconductor integrated circuit microelectronic fabrications. More particularly, the present invention relates to vertical split gate field effect transistor (FET) devices, as fabricated within semiconductor integrated circuit microelectronic fabrications.
2. Description of the Related Art
In addition to conventional semiconductor integrated circuit microelectronic fabrications having fabricated therein conventional field effect transistor (FET) devices and conventional bipolar junction transistor (BJT) devices whose transient operation provides for data storage and transduction capabilities within the conventional semiconductor integrated circuit microelectronic fabrications, there also exists within the art of semiconductor integrated circuit microelectronic fabrication non-volatile semiconductor integrated circuit microelectronic fabrications, and in particular non-volatile semiconductor integrated circuit microelectronic memory fabrications, such as but not limited to electrically erasable programable read only memory (EEPROM) non-volatile semiconductor integrated circuit microelectronic memory fabrications, whose data storage and transduction capabilities are not predicated upon transient operation.
Although non-volatile semiconductor integrated circuit microelectronic memory fabrications, such as but not limited to electrical erasable programmable read only memory (EEPROM) non-volatile semiconductor integrated circuit microelectronic memory fabrications, may be fabricated while employing any of several semiconductor integrated circuit microelectronic devices, a particularly common semiconductor integrated circuit microelectronic device fabricated within an electrically erasable programmable read only memory (EEPROM) non-volatile semiconductor integrated circuit microelectronic memory fabrication is a split gate field effect transistor (FET) device.
A split gate field effect transistor (FET) device is in part analogous in structure and operation with a conventional field effect transistor (FET) device insofar as a split gate field effect transistor (FET) device also comprises formed within a semiconductor substrate a channel region defined by a pair of source/drain regions also formed within the semiconductor substrate, wherein at least the channel region of the semiconductor substrate has formed thereupon a gate dielectric layer which separates a gate electrode from the channel region of the semiconductor substrate, but a split gate field effect transistor (FET) device is nonetheless distinguished from a conventional field effect transistor (FET) device by employing rather than a single gate electrode positioned upon the gate dielectric layer and completely covering the channel region of the semiconductor substrate: (1) a floating gate electrode positioned upon the gate dielectric layer and covering over only a portion of the channel region defined by the pair of source/drain regions (such portion of the channel region also referred to as a floating gate electrode channel region); and (2) a control gate electrode positioned over the gate dielectric layer and covering a remainder portion of the channel region while at least partially covering and overlapping the floating gate electrode while being separated from the floating gate electrode by an intergate electrode dielectric layer (such remainder portion of the channel region also referred to as a control gate electrode channel region).
In order to effect operation of a split gate field effect transistor (FET) device, particular sets of voltages are applied to the control gate electrode, the source/drain regions and the semiconductor substrate in order to induce charge, reduce charge or sense charge within the floating gate electrode (which is otherwise fully electrically isolated) and thus provide conditions under which the floating gate electrode within the split gate field effect transistor (FET) device may be programmed, erased and/or read.
While split gate field effect transistor (FET) devices are thus desirable within the art of semiconductor integrated circuit microelectronic fabrication for providing semiconductor integrated circuit microelectronic fabrications with non-volatile data storage characteristics, split gate field effect transistor (FET) devices are nonetheless not entirely without problems in the art of semiconductor integrated circuit microelectronic fabrication for providing semiconductor integrated circuit microelectronic fabrication with non-volatile data storage characteristics.
In that regard, it is known in the art of semiconductor integrated circuit microelectronic fabrication that split gate field effect transistor (FET) devices are often difficult to fabricate with enhanced areal density and enhanced performance, in part since split gate field effect transistor (FET) devices are fabricated with generally enlarged multi-region channel regions within semiconductor substrates.
It is thus desirable within the art of semiconductor integrated circuit microelectronic fabrication, and in particular within the art of semiconductor integrated circuit microelectronic memory fabrication, to provide split gate field effect transistor (FET) devices with enhanced areal density and enhanced performance.
It is towards the foregoing objects that the present invention is directed.
Various non-volatile semiconductor integrated circuit microelectronic fabrications having formed therein associated semiconductor integrated circuit microelectronic devices with enhanced areal density, as well as methods for fabrication thereof, have been disclosed within the art of non-volatile semiconductor integrated circuit microelectronic fabrication.
Generally, such non-volatile semiconductor integrated circuit microelectronic fabrications have formed therein non-volatile semiconductor integrated circuit microelectronic devices at least portions of which are formed within trenches within semiconductor substrates which comprise the non-volatile semiconductor integrated circuit microelectronic fabrications.
Examples of such non-volatile semiconductor integrated circuit microelectronic fabrications having fabricated therein non-volatile semiconductor integrated circuit microelectronic devices at least portions of which are formed within trenches within semiconductor substrates which comprise the non-volatile semiconductor integrated circuit microelectronic fabrications are disclosed within, but not limited to: (1) Hong (U.S. Pat. No. 5,703,387) (a non-volatile semiconductor integrated circuit microelectronic fabrication having fabricated therein a split gate field effect transistor (FET) device having a floating gate electrode which is formed covering completely a sidewall of a trench within a semiconductor substrate); (2) Jung Lin et al. (U.S. Pat. No. 6,087,222) (a non-volatile semiconductor integrated circuit microelectronic fabrication having fabricated therein a split gate field effect transistor (FET) device having a floating gate electrode covering only a portion of a sidewall of a trench within a semiconductor substrate); (3) Lin et al. (U.S. Pat. No. 6,093,006) (a non-volatile semiconductor integrated circuit microelectronic fabrication having fabricated therein a stacked gate field effect transistor (FET) device having a floating gate electrode covering completely a sidewall of a trench within a semiconductor substrate); and (4) Mei et al. (U.S. Pat. No. 6,130,453) (a non-volatile semiconductor integrated circuit microelectronic fabrication having fabricated therein a split gate field effect transistor (FET) device having a floating gate electrode covering completely and extending above a sidewall of a trench within a semiconductor substrate).
Desirable within the art of non-volatile semiconductor integrated circuit microelectronic fabrication, and in particular within the art of non-volatile semiconductor integrated circuit microelectronic memory fabrication, are additional methods and materials which may be employed for forming split gate field effect transistor (FET) devices with enhanced areal density and enhanced performance.
It is towards the foregoing objects that the present invention is directed.
A first object of the present invention is to provide for use within a semiconductor integrated circuit microelectronic fabrication a split gate field effect transistor (FET) device, and a method for fabricating the split gate field effect transistor (FET) device.
A second object of the present invention is to provide the split gate field effect transistor (FET) device and the method for fabricating the split gate field effect transistor (FET) device in accord with the first object of the present invention, wherein the split gate field effect transistor (FET) device is fabricated with enhanced areal density and enhanced performance.
A third object of the present invention is to provide the split gate field effect transistor (FET) device and the method for fabricating the split gate field effect transistor (FET) device in accord with the first object of the present invention and the second object of the present invention, wherein the method for fabricating the split gate field effect transistor (FET) device is readily commercially implemented.
In accord with the objects of the present invention, there is provided by the present invention a split gate field effect transistor (FET) device and a method for fabricating the split gate field effect transistor (FET) device. To practice the method of the present invention, there is first provided a semiconductor substrate having formed therein a trench. There is also formed within: (1) an upper portion of the semiconductor substrate which includes an upper portion of a sidewall of the trench; and (2) a lower portion of the semiconductor substrate which includes a floor of the trench, a pair of source/drain regions which is separated by a lower portion of the sidewall of the trench which defines a channel region. There is also formed covering at least the channel region but not filling the trench a gate dielectric layer. There is then formed upon the gate dielectric layer and covering only a lower sub-portion of the channel region and not an upper sub-portion of the channel region a floating gate electrode. There is then formed upon the floating gate electrode an intergate electrode dielectric layer. Finally, there is then formed upon the intergate electrode dielectric layer a control gate electrode which vertically and horizontally overlaps within the trench the floating gate electrode and covers within the trench the upper sub-portion of the channel region.
Within the present invention xe2x80x9ccoveringxe2x80x9d is intended to include covering in a vertical direction and, more particularly, covering in a horizontal direction.
The method for fabricating the split gate field effect transistor (FET) device in accord with the present invention contemplates a split gate field effect transistor (FET) device fabricated in accord with the method for fabricating the split gate field effect transistor (FET) device in accord with the present invention.
The present invention provides for use within a semiconductor integrated circuit microelectronic fabrication a split gate field effect transistor (FET) device, and a method for fabricating the split gate field effect transistor (FET) device, wherein the split gate field effect transistor (FET) device is fabricated with enhanced areal density and enhanced performance.
The present invention realizes the enhanced areal density of the split gate field effect transistor (FET) device by fabricating the split gate field effect transistor (FET) device with a channel region contained completely within a trench within a semiconductor substrate within which is fabricated the split gate field effect transistor (FET) device. The present invention realizes the enhanced performance of the split gate field effect transistor (FET) device in part by forming within the trench and covering only a lower sub-portion of the channel region a floating gate electrode which in turn has formed vertically and horizontally overlapping thereover within the trench a control gate electrode which covers an upper sub-portion of the channel region within the trench.
The method for fabricating the split gate field effect transistor (FET) device in accord with the present invention is readily commercially implemented.
The present invention employs methods and materials as are generally known in the art of semiconductor integrated circuit microelectronic fabrication, but employed within the context of a specific process ordering and specific series of process limitations to provide a split gate field effect transistor (FET) device in accord with the present invention. Since it is thus a specific process ordering and a specific series of process limitations which provides at least in part the present invention, rather than the existence of methods and materials which provides the present invention, the method for fabricating the split gate field effect transistor (FET) device in accord with the present invention is readily commercially implemented.